A literal explosion of personal electronic devices has fostered frenzy of integrated circuit development and technology development. The demand for digital cameras in our cellular telephones has now expanded to include adding digital video recorders, global positioning systems, personal video players, and high quality audio. The integration of these functions makes power management and isolation a requirement for proper circuit operation.
Trenched isolation regions are commonly utilized for electrically isolating section adjacent structures in highly integrated semiconductor constructions. A common form of trenched isolation region is a so-called shallow trench isolation (STI) region.
STI isolation is an indispensable technique for deep sub-micron and nanometer CMOS circuit designs. However, it is known that an STI isolated transistor inherently has two parasitic STI edge transistors that may be formed where the gate oxide extends over the edge of the trench isolation regions on either side of the intended transistor.
A difficulty which can occur when utilizing the trenched isolation region adjacent to a transistor structure is that any sharp active corner at the trenched isolation region edge can lead to a high fringing electric field, which can establish a parasitic transistor with a lower threshold voltage (Vth) along the trench edge in parallel to the intended transistor.
An edge parasitic transistor with a lower Vth provides a leakage path even before the intended transistor is turned “on.” This can lead to numerous problems during operation of the intended transistor, and can manifest as a “double hump” in the sub-threshold characteristics of the intended transistor. The uncontrolled parasitic transistor may send an uncontrolled amount of current to an incorrect destination. Such unintended current paths may destroy the unintended destination device due to the excessive current from the parasitic transistor.
The double hump issue is a sign that unintended parasitic transistors are conducting current. In some cases they can cause intermittent errors because as the intended transistor is activated, the parasitic transistors may reinforce or resist the intended current flow. The low ebb of the double hump may cause erroneous power resets to be generated or detected. The double hump issue can be worse for high-voltage devices due to lower well concentration and higher operating voltage. Early field failures due to the operation of the parasitic transistors can cost original equipment manufacturers millions of dollars to repair.
Another problem that can occur with field oxide is thinning of the field oxide at corners under transistor gates. The thinning can occur due to thermal oxide tending to not grow as thick on the corners as in the central region of the field oxide. The thinning of the field oxide at the corners can exacerbate the fringing electric field problems discussed above, and can lead to decreased reliability of the oxide.
An example of such problems may be a high voltage NMOS transistor having a sub-threshold curve that has no obvious hump at zero body bias. With the increase of body bias, the double hump may appear and become increasingly worse. For an advanced low voltage transistor, the double hump may appear even at zero body bias and a great amount of effort has gone into optimizing the corner rounding process for trench isolation regions.
Numerous approaches have been developed for attempting to alleviate problems associated with sharp active corners at trenched isolation region edges, but such approaches have not yet proven to be fully satisfactory. Accordingly, it would be desirable to develop new methodologies for alleviating problems associated with sharp active corners at trenched isolation region edges.
Thus, a need still remains for an integrated circuit system with high voltage transistor that can relieve the leakage current problems associated with shallow trench isolation. In view of the increasing demand for multiple function integration, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.